Semiconductor device, solid-state image pickup element, imaging device, and electronic apparatus

ABSTRACT

The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.

TECHNICAL FIELD

The present technology relates to a semiconductor device, a solid-stateimage pickup element, an imaging device, and an electronic apparatus,and more particularly to a semiconductor device, a solid-state imagepickup element, an imaging device, and an electronic apparatus which cansuppress characteristic fluctuations caused by capacitance fluctuationsdue to a dummy wire, while maintaining an affixing bonding strength bythe dummy wire, for a device configured by affixing a plurality of chipstogether to laminate.

BACKGROUND ART

As a technology for manufacturing a laminated semiconductor device bybonding two or more semiconductor chips, a wiring layer is formed on abonding surface between both chips and the chips are affixed together atthe wiring layer on the bonding surface so as to be electricallyconnected.

In the case of a solid-state image pickup element, a configuration isadopted in which, by affixing a wafer having a photoelectric conversionunit formed thereon and a wafer including a circuit configured toperform signal processing, via an electrical connection unit, a signalis transmitted to a signal processing circuit from the photoelectricconversion unit via a wiring unit on an affixed surface.

As such a technology for the solid-state image pickup element, there isproposed a technology in which a true connection wiring unitelectrically connected to a portion where a photoelectric conversionunit is formed and a dummy wire not electrically connected a portionother than the portion where the photoelectric conversion unit is formedare formed on an affixed surface and the true connection wiring unit andthe dummy wire are arranged at the same interval, such that yield at thetime of manufacture is improved (refer to Patent Document 1).

CITATION LIST Patent Document

-   Patent Document 1: Japanese Patent Application Laid-Open No.    2013-168623

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

Incidentally, in the case of affixing wiring layers, there is a need tokeep the coverage of metal on a bonding surface within a predeterminedrange in order to maintain the flatness of the bonding surface and theaffixing strength thereof. It has been therefore proposed to arrange adummy wire on the bonding surface in order to keep the coverage of themetal within a predetermined range.

However, in the case of a solid-state image pickup element, a phenomenonthat the dummy wire located within a pixel is reflected in an outputimage sometimes occurs. This phenomenon is assumed to be caused byfluctuations of the parasitic capacitance of each pixel arising due tothe coupling between the dummy wires depending on the arrangement of thedummy wires.

As long as a device is constituted by chips laminated on each other,characteristic fluctuations caused by capacitance fluctuations arise dueto the coupling of the dummy wires even for devices other than thesolid-state image pickup element. For example, a case where a flashmemory or the like is formed in a laminated structure, there is apossibility that the characteristic varies from one cell to another dueto the dummy wire and it becomes difficult to perform an appropriateaction.

The present technology has been made in view of such a situation and, inparticular, it is an object of the present technology to enable thesuppression of characteristic fluctuations caused by capacitancefluctuations due to a dummy wire, while an affixing bonding strength ofchips is maintained by the dummy wire, for a device configured byaffixing a plurality of chips together to laminate.

Solutions to Problems

A semiconductor device according to an aspect of the present technologyincludes two or more chips in which wires that are electricallyconnected are formed on bonding surfaces and the bonding surfacesopposing each other are bonded to be laminated, and in the semiconductordevice, with respect to a region where the wires are periodically andrepeatedly disposed in predetermined units, a dummy wire is disposed onthe bonding surface at a pitch corresponding to the predetermined unit.

The semiconductor device can be a solid-state image pickup element, inwhich, with respect to a region where the wires are periodically andrepeatedly disposed in predetermined units for a pixel of thesolid-state image pickup element, the dummy wire is disposed on thebonding surface at a pitch corresponding to the predetermined unit.

It is possible to make the dummy wire disposed on one of the bondingsurfaces opposing each other and the dummy wire disposed on another ofthe bonding surfaces opposing each other have substantially the samepattern.

It is possible to make the dummy wire disposed on one of the bondingsurfaces opposing each other and the dummy wire disposed on another ofthe bonding surface opposing each other have different patterns.

The predetermined unit for the pixel of the solid-state image pickupelement can be a plurality of the pixels sharing a contact of the samefloating diffusion.

The predetermined unit for the pixel of the solid-state image pickupelement can be a plurality of the pixels sharing the same floatingdiffusion.

The predetermined unit for the pixel of the solid-state image pickupelement can be a single one of the pixels.

With respect to a region where the wires are periodically and repeatedlydisposed in the predetermined units for the pixel of the solid-stateimage pickup element, a real wire can be disposed along with the dummywire on the bonding surface at a pitch corresponding to thepredetermined unit.

An electrode to which a predetermined voltage is applied can beincluded, and the dummy wire can be fixed to the predetermined voltageapplied from the electrode.

A solid-state image pickup element according to an aspect of the presenttechnology includes two or more chips in which wires that areelectrically connected are formed on bonding surfaces and the bondingsurfaces opposing each other are bonded to be laminated, and in thesolid-state image pickup element, with respect to a region where thewires are periodically and repeatedly disposed in predetermined unitsfor a pixel, the dummy wire is disposed on the bonding surface at apitch corresponding to the predetermined unit.

An imaging device according to an aspect of the present technologyincludes two or more chips in which wires that are electricallyconnected are formed on bonding surfaces and the bonding surfacesopposing each other are bonded to be laminated, and in the imagingdevice, with respect to a region where the wires are periodically andrepeatedly disposed in predetermined units for a pixel, the dummy wireis disposed on the bonding surface at a pitch corresponding to thepredetermined unit.

An electronic apparatus according to an aspect of the present technologyincludes two or more chips in which wires that are electricallyconnected are formed on bonding surfaces and the bonding surfacesopposing each other are bonded to be laminated, and in the electronicapparatus, with respect to a region where the wires are periodically andrepeatedly disposed in predetermined units for a pixel, the dummy wireis disposed on the bonding surface at a pitch corresponding to thepredetermined unit.

In an aspect of the present technology, two or more chips in which wiresthat are electrically connected are formed on bonding surfaces and thebonding surfaces opposing each other are bonded to be laminated areincluded, and with respect to a region where the wires are periodicallyand repeatedly disposed in predetermined units for a pixel, the dummywire is disposed on the bonding surface at a pitch corresponding to thepredetermined unit.

Effects of the Invention

According to an aspect of the present technology, characteristicfluctuations caused by capacitance fluctuations due to a dummy wire canbe suppressed, while an affixing bonding strength of chips is maintainedby the dummy wire, for a device configured by affixing a plurality ofchips together to laminate.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram for explaining a circuit configuration example of asolid-state image pickup element to which the present technology isapplied.

FIG. 2 is a view for explaining a side cross section of a configurationexample according to a first embodiment of the solid-state image pickupelement to which the present technology is applied.

FIG. 3 is a diagram for explaining a disposition pattern of dummy wiresof the solid-state image pickup element in FIG. 2.

FIG. 4 is a diagram for explaining a configuration example according toa second embodiment of the solid-state image pickup element to which thepresent technology is applied.

FIG. 5 is a diagram for explaining a configuration example according toa third embodiment of the solid-state image pickup element to which thepresent technology is applied.

FIG. 6 is a view for explaining a side cross section of a configurationexample of the solid-state image pickup element in FIG. 5.

FIG. 7 is a diagram for explaining a configuration example according toa fourth embodiment of the solid-state image pickup element to which thepresent technology is applied.

FIG. 8 is a diagram for explaining a configuration example according toa fifth embodiment of the solid-state image pickup element to which thepresent technology is applied.

FIG. 9 is a diagram for explaining a configuration example according toa sixth embodiment of the solid-state image pickup element to which thepresent technology is applied.

FIG. 10 is a diagram for explaining a configuration example according toa seventh embodiment of the solid-state image pickup element to whichthe present technology is applied.

FIG. 11 is a diagram for explaining points of the solid-state imagepickup element to which the present technology is applied.

FIG. 12 is a diagram for explaining a technique for reducing theinfluence of characteristic fluctuations used by the solid-state imagepickup element to which the present technology is applied.

FIG. 13 is a diagram for explaining an application example of asemiconductor device to which the present technology is applied.

FIG. 14 is a diagram for explaining a configuration of an imaging deviceand an electronic apparatus using the solid-state image pickup elementto which the present technology is applied.

FIG. 15 is a diagram illustrating an example of use of the solid-stateimage pickup element.

MODE FOR CARRYING OUT THE INVENTION

Examples of best modes for carrying out the present invention will bedescribed hereinafter but the present invention is not limited to thefollowing examples.

First Embodiment

<Circuit Configuration Example of Solid-State Image Pickup Element>

Next, referring to FIG. 1, a circuit configuration example of asolid-state image pickup element to which the present technology isapplied will be described. FIG. 1 illustrates an example of a circuitconfiguration constituting the solid-state image pickup element to whichthe present technology is applied.

The circuit configuration example of the solid-state image pickupelement in FIG. 1 includes a reset transistor TR11, transfer transistorsTR12-1 to TR12-8, an amplification transistor TR13, a selectiontransistor TR14, a floating diffusion FD (hereinafter also simplyreferred to as FD), photodiodes PD1 to PD8 (hereinafter also simplyreferred to as PD1 to PD8), and a vertical transfer line VLINE.

The solid-state image pickup element in FIG. 1 is a solid-state imagepickup element including a total of four types of transistors, namely,the reset transistor TR11, the transfer transistors TR12-1 to TR12-8,the amplification transistor TR13, and the selection transistor 14 andthus categorized particularly as a solid-state image pickup elementcalled a 4TR type (4-transistor type). Note that, in the present workingexample, explanation will be made by taking the 4TR type solid-stateimage pickup element as an example, but other configurations may beadopted. For example, a 3TR type solid-state image pickup elementconstituted by the three types of transistors except the selectiontransistor TR14 may be employed.

The PD1 to the PD8 generate charges corresponding to the amount ofincident light through photoelectric conversion and accumulate thegenerated charges.

The transfer transistors TR12-1 to TR12-8 are transistors that open andclose according to a transfer signal and are turned on in a case wherethe transfer signal is at a high level to transfer the chargesaccumulated in the PD1 to the PD8 to the FD.

The FD accumulates the charges transferred from the PD1 to the PD8 viathe transfer transistors TR12-1 to TR12-8, according to open/closedstates of the reset transistor TR11 and the amplification transistorTR13.

The reset transistor TR11 is a transistor that opens and closesaccording to a reset signal and is turned on in a case where the resetsignal is at a high level to discharge the charges accumulated in the FDto a drain D.

The amplification transistor TR13 is a transistor controlled by an inputvoltage corresponding to the charges accumulated in the FD and amplifiesthe voltage applied from a drain D′ with the input voltage correspondingto the charges accumulated in the FD to output to the selectiontransistor TR14 as a pixel signal.

The selection transistor TR14 is a transistor that is opened and closedaccording to a selection control signal and controlled to be turned onwhen the selection control signal is at the high level and outputs thepixel signal output from the amplification transistor TR13 to thevertical transfer line VLINE.

That is, by turning on the reset transistor TR11 and the transfertransistors TR12-1 to TR12-8, the PD1 to the PD8 and the FD are reset.

Next, when the reset transistor TR11 and the transfer transistors TR12-1to TR12-8 are turned off, exposure states of the PD1 to the PD8 arereached and a charge corresponding to the amount of incident light isgenerated through photoelectric conversion sequentially in the PD1 tothe PD8 to be accumulated.

Here, when one of the transfer transistors TR12-1 to TR12-8 is turnedon, the charges accumulated in corresponding one of the PD1 to the PD8are transferred to the FD.

At this time, a voltage corresponding to the charges accumulated in oneof the PD1 to the PD8 and transferred to the FD is input to a gate ofthe amplification transistor TR13 such that the amplification transistorTR13 amplifies a voltage applied by a drain terminal D′ to output to theselection transistor TR14 as the pixel signal.

Subsequently, when the selection transistor TR14 is turned on by aselection signal, the pixel signal output from the amplificationtransistor TR13 is output to the vertical transfer line VLINE.

Thereafter, the PD1 to the PD8 are sequentially switched such that thepixel signals equivalent to eight pixels are sequentially switched to beoutput.

Here, FIG. 1 illustrates a circuit configuration example in which thetransfer transistors TR12-1 to 12-8 are provided for the same FD so asto connect cathodes of the PD1 to the PD8 between sources and drains.

That is, FIG. 1 illustrates a circuit configuration when eight pixels ofthe PD1 to the PD8 are shared by one FD.

With such a configuration, for example, while the transfer transistorsTR12-2 to TR12-8 are kept in an off state, the FD can be used for onepixel of the PD1 by controlling the transfer transistor TR12-1 to beturned on or off. Similarly, by sequentially switching turning on andoff of the transfer transistors TR12-2 to TR12-8, the FD can be used bybeing switched for each of the PD1 to the PD8. As a result, eight-pixelsharing in which one FD (including the reset transistor TR11, theamplification transistor TR13, the selection transistor TR14, and thevertical transfer line VLINE) is shared by eight pixels, which issurrounded by a two-dot chain line in FIG. 1, is realized.

Additionally, for example, as indicated by a range surrounded by aone-dot chain line in FIG. 1, four-pixel sharing in which one FD isshared by four pixels is realized with a configuration only includingthe transfer transistors TR12-1 to 12-4 and the PD1 to the PD4 inaddition to one reset transistor TR11, one amplification transistorTR13, one selection transistor TR14, and one vertical transfer lineVLINE.

Furthermore, other number of PDs can be realized as well by connectingthe PDs to a common FD via the transfer transistor.

Note that, in the following description, a group of a plurality ofpixels using one FD by sharing as described above will be referred to asa sharing unit. Therefore, in FIG. 1, the range surrounded by theone-dot chain line is a sharing unit for realizing the four-pixelsharing, while the range surrounded by the two-dot chain line is asharing unit for realizing the eight-pixel sharing.

<Layout of Solid-State Image Pickup Element>

FIGS. 2 and 3 are diagrams for explaining a layout of the solid-stateimage pickup element to which the present technology is applied. FIG. 2is a side cross-sectional view, whereas FIG. 3 is a top view. In moredetail, the cross-sectional view in FIG. 2 illustrates a side crosssection of a portion indicated by a dotted line in FIG. 3.

The solid-state image pickup element 11 in FIG. 2 is constituted by alens layer 31, a color filter layer 32, a light shielding wall layer 33,a photoelectric conversion layer 34, and wiring layers 35 and 36 fromabove.

The lens layer 31 transmits incident light, which is light incident fromthe upper side in FIG. 2, such that the incident light condenses in thephotoelectric conversion layer 34 so as to be focused.

The color filter layer 32 transmits only light of a specific wavelengthamong the incident light having passed through the lens image 31 inpixel units. In more detail, for example, the color filter layer 32extracts light having wavelengths corresponding to light of colors suchas R, G (Gr and Gb), and B (red, green, and blue) as illustrated in FIG.3, in pixel units to transmit.

The light shielding wall layer 33 is a layer on which a light shieldingwall 33 a is provided and this light shielding wall 33 a shieldsincident light from adjacent pixels such that light in pixel unitsformed for each convex portion in the lens layer 31 in FIG. 1 is onlyincident on a PD in the photoelectric conversion layer 34 correspondingto a pixel immediately below each convex portion.

The photoelectric conversion layer 34 is a layer on which theabove-described PD1 to PD8 serving as the pixel units are formed andgenerates a charge corresponding to the amount of incident light throughphotoelectric conversion to transfer the generated charge to the FD viathe transfer transistor TR12 provided in the wiring layer.

The wiring layer 35 is provided with the reset transistor TR11, thetransfer transistor TR12, the amplification transistor TR13, theselection transistor TR14, the FD, and the drains D and D′ and outputsthe pixel signal to a real wire (a wire through which a signal isactually transmitted) (not illustrated) of the wiring layer 36 via areal wire (not illustrated). Meanwhile, dummy wires 35 a and 35 b madeof copper (Cu) are provided within the wiring layer 35 in FIG. 2 at thesame pitch as an FD contact to reinforce the strength generated from thebonding of the wiring layers 35 and 36.

The wiring layer 36 is provided with a circuit for processing the pixelsignal input from the real wire (not illustrated) of the wiring layer 36via the real wire (not illustrated) of the wiring layer 35. In addition,as in the case of the wiring layer 35, the wiring layer 36 also hasdummy wires 36 a and 36 b provided at the same pitch as the FD contact.

The wiring layers 35 and 36 are formed in a state where the wiringlayers 35 and 36 are affixed together and electrically connected to eachother with a bonding surface F as a boundary via the real wires (notillustrated) and the respective wiring layers 35 and 36 are formed asseparate chips (wafers) in an initial stage of manufacturing.Additionally, while the dummy wires 35 a and 36 a are affixed togetherat the bonding surface F, the dummy wires 35 b and 36 b arerepresentative of all dummy wires other than the dummy wires 35 a and 36a. Therefore, in the wiring layers 35 and 36 in FIG. 2,quadrangular-shaped structures not labeled are all included in the dummywires 35 b and 36 b.

In the solid-state image pickup element 11 illustrated in FIGS. 2 and 3,a total of eight pixels of two pixels×four pixels are set as a sharingunit. In more detail, the sharing unit is set with eight pixels in sucha manner that four-pixel unit portions each made up of an R pixel, a Grpixel, a Gb pixel, and a B pixel illustrated within a heavy line at theupper left in FIG. 3 are disposed above and below each other. Inaddition, in the example in FIG. 3, the FD contacts (not illustrated)are provided so as to be electrically connected to the FDs at therespective central positions of upper two pixels×two pixels and lowertwo pixels×two pixels within the sharing unit made up of theabove-mentioned eight pixels.

Since the dummy wires 35 a and 36 a are arranged at the same pitch asthis FD contact, a pixel unit indicated by the convex portion in thelens layer 31 in the cross section in FIG. 2 is set in units of twopixels indicated by P.

As illustrated in the lower part of FIG. 3, the FD contact is an FDcontact C electrically connected to the FD provided on an output side ofthe transfer transistors TR12-1 to TR12-4 which transfer correspondingcharges when respective pixels of two pixels×two pixels are constitutedby the PD1 to the PD4. As illustrated in the lower part of FIG. 3, theFD contact C is provided at the center position with respect to thelayout of two pixels×two pixels. Accordingly, in the example in theupper part of FIG. 3, the pitch of two pixels×two pixels with respect toa horizontal direction×a vertical direction is defined as an FD contactpitch.

Therefore, the upper part of FIG. 3 illustrates that the dummy wires 35a and 36 a corresponding to a dummy wire D are arranged in the wiringlayers 35 and 36 in a quadrangular shape at a similar pit as the FDcontact pitch of two pixels×two pixels.

Similarly, the dummy wires 35 a and 35 b and the dummy wires 36 a and 36b are all arranged at equal intervals by the pitch of the FD contacts.In other words, a pitch at which the dummy wires 35 a and the dummywires 36 b are both arranged is the same as a pitch at which the FDcontact C is arranged.

By disposing the dummy wire D as illustrated in FIG. 3, the parasiticcapacitance arising due to the coupling between the dummy wires 35 a and36 a can be made the same in each pixel. Note that, needless to say, thesame applies to a parasitic capacitance arising due to the couplingbetween other dummy wires.

As a result, characteristic fluctuations caused by capacitancefluctuations due to the dummy wire can be suppressed, while an affixingbonding strength of wafers is maintained by that dummy wire, for adevice configured by affixing a plurality of chips together to laminate.

In addition, in FIG. 2, although a symbol of a capacitor is given in thewiring layer 35 such that the dummy wire 35 a and the dummy wire 35 bserves as end portions, this is not intended to indicate the presence ofa capacitor as a practical case but schematically represents theparasitic capacitance arising due to the coupling between the dummy wire35 a and the dummy wire 36 b.

Second Embodiment

The above description has used an example in which the dummy wire isdisposed at a pitch similar to the pitch of the FD contact. By disposingthe dummy wire at the pitch of the FD contact, practically, theparasitic capacitance arising due to coupling is made the same in eachpixel. Therefore, the dummy wire can achieve a similar effect even witha dummy wire at the pitch of the FD contact but in another shape in eachpixel.

FIG. 4 illustrates a configuration example of the solid-state imagepickup element in which, in two pixels×two pixels where the FD contactis formed at the center thereof, the dummy wire D is disposed so as tobe point-symmetrical with respect to the horizontal direction and thevertical direction using a position where the FD contact is arranged asthe center.

In more detail, as illustrated in FIG. 4, dummy wires D1 and D2 havingoctagonal shapes are provided at a central portion where the FD contactfor two pixels×two pixels is arranged and at respective positionsserving as the vertexes of an octagon concentric with that centralportion.

The dummy wire D1 in FIG. 4 corresponds to the dummy wire 35 a in FIG.2, whereas the dummy wire D2 corresponds to the dummy wire 36 a in FIG.2.

Each of the dummy wires D1 and D2 has an octagonal shape and the dummywire D2 has an octagonal shape with a diameter somewhat larger than thatof the dummy wire D1. In addition, a total of nine dummy wires D1 and D2are disposed in the range of two pixels×two pixels where the FD contactis disposed at the center position, in such a manner that one wire isdisposed at the center position, which is the position where the FDcontact is disposed, and eight wires are disposed at the positions ofeight vertexes when an octagon is formed concentrically with respect tothe center position.

By disposing the dummy wires D1 and D2 in this manner, the dummy wiresD1 and D2 are disposed point-symmetrically within the multiple pixels oftwo pixels×two pixels where the FD contact is disposed at the centerposition. As a result, characteristic fluctuations caused by theparasitic capacitance due to the coupling between the dummy wires D1 andD2 can be made the same in every pixel.

Note that the shape and the number of the dummy wires are not limited aslong as the dummy wires D1 and D2 are arranged at the pitch of the FDcontact and disposed point-symmetrically using the FD contact as thecenter within two pixels×two pixels in which a position where the FDcontact is disposed is used as the center and this FD contact is sharedthereamong. In addition, the dummy wire D1 corresponding to the dummywire 35 a on an upper chip side and the dummy wire D2 corresponding tothe dummy wire 36 a on a lower chip side may have the same size as eachother or different sizes from each other. It is possible to suppresscharacteristic fluctuations caused by capacitance fluctuations due tothe dummy wire, while an affixing bonding strength of wafers ismaintained, for a device configured by affixing a plurality of chipstogether to laminate.

Third Embodiment

The above description has used an example in which, by repeatedlydisposing the dummy wires D (or D1 and D2) at the same positions asthose of the FD contacts at the pitch thereof, characteristicfluctuations caused by capacitance fluctuations arising due to thecoupling between the disposed dummy wires are suppressed. However, aslong as the capacitance fluctuations arising due to the coupling betweenthe dummy wires are the same, characteristic fluctuations can besuppressed even if the dummy wires are disposed by another method. Forexample, as illustrated in FIG. 5, the dummy wire D may be disposed in ashape that matches in the sharing units by the FD such that a fixedpotential is applied to the dummy wire D.

That is, in the solid-state image pickup element in FIG. 5, the dummywire D is disposed in a band shape in the vertical direction in thevicinity of the center of a sharing unit of two pixels×four pixels inthe horizontal direction, while being disposed in a band shape in thehorizontal direction in the vicinity of the center of a sharing unit oftwo pixels×four pixels in the vertical direction, whereby the dummywires D are disposed in a lattice pattern.

The upper part of FIG. 6 is a top view of a chip constituting thesolid-state image pickup element in FIG. 5, whereas the lower part ofFIG. 6 is a side cross section of a dotted line portion in FIG. 5. Asillustrated in the upper part of FIG. 6, a central range of the chip isan effective region A of the solid-state image pickup element andelectrodes B are provided around this range. In addition, as illustratedin the side cross section of the dotted line portion of FIG. 5 in thelower part of FIG. 6, the dummy wires 35 a and 36 a are formed so as tobe continuously connected in the horizontal direction in FIG. 6.

As illustrated in the lower part of FIG. 6, a right side portion Z1where the lens layer 31 is formed is a portion corresponding to theeffective region A, whereas a left side portion Z2 in FIG. 6 where thelens layer 31 is formed is a region other than the effective region A(non-effective region). That is, the portion Z1 in the lower part ofFIG. 6 corresponds to the effective region A in the upper part of FIG.6. In the lower part of FIG. 6, a power supply contact E is provided ina range belonging to the portion Z2 on the dummy wire 35 a and the powersupply contact E is connected to the electrode B in the upper part ofFIG. 6. With such a configuration, the potentials of the dummy wires 35a and 36 a are set to a fixed potential.

That is, by disposing the dummy wires D in a lattice pattern in a planardirection as illustrated by the dummy wires D in FIG. 5 and also using alaminated configuration as illustrated by the dummy wires 35 a and 36 a(=the dummy wire D) in FIG. 6, the dummy wire D (35 a and 36 a) is setto a fixed potential. With such a configuration, characteristicfluctuations caused by capacitance fluctuations corresponding to theparasitic capacitance arising due to the coupling of the dummy wires canbe made the same in sharing units each made up of two pixels×fourpixels.

As a result, it is possible to suppress characteristic fluctuationscaused by capacitance fluctuations due to the dummy wire, while anaffixing bonding strength of wafers is maintained, for a deviceconfigured by affixing a plurality of chips together to laminate. Notethat the power supply contact E may be provided at either of the portionZ1 which is the effective region A and the portion Z2 which is thenon-effective region and may be connected to either of the dummy wires35 a and 36 a. Alternatively, a configuration in which the connection bythe power supply contact E is not provided and the potential is notfixed may be adopted. In addition, the dummy wire D may have not only alattice pattern as illustrated in FIG. 5 but also a configuration withonly stripes in the horizontal direction or only stripes in the verticaldirection. Furthermore, the dummy wire is not limited to being disposedin such a manner that the dummy wires are provided on the entire surfaceand rectangular shapes are removed therefrom as in the lattice patternin FIG. 5, but may be disposed by cropping out another shape. Forexample, a lattice pattern obtained by cropping out square shapes fromthe dummy wires provided on the entire surface may be adopted.

Fourth Embodiment

The above description has used an example in which the dummy wires 35 aand 36 a in the wiring layers 35 and 36 all have substantially the sameshape and are arranged at substantially the same position, but the dummywires 35 a and 36 a may be disposed in different shapes and at differentpositions as long as the dummy wires 35 a and 36 a are individuallyarranged at the pitch of the FD contact.

FIG. 7 illustrates a configuration example of the solid-state imagepickup element in which the dummy wires 35 a and 36 a are disposed indifferent shapes and at different positions.

More specifically, in FIG. 7, each of the dummy wires D1 correspondingto the dummy wires 35 a is disposed in a square shape at a positionshifted from the center position of the range of two pixels×two pixelssharing the same FD contact by the same distance in the same direction.Meanwhile, the dummy wire D2 corresponding to the dummy wire 36 a isdisposed such that a square is cut out from the range of two pixels×twopixels having a common FD contact.

As described above, the dummy wire D1 corresponding to the dummy wire 35a of an upper side chip and the dummy wire 36 a corresponding to thedummy wire 36 a of a lower side chip may have different shapes andpositions on the bonding surface F. However, in this case, as long asthe dummy wires D1 and D2 are individually disposed in the same shapeand at the same position within the range of two pixels×two pixelssharing the FD contact, it is possible to suppress characteristicfluctuations caused by capacitance fluctuations due to the dummy wire,while an affixing bonding strength of wafers is maintained, for a deviceconfigured by affixing a plurality of chips together to laminate.Incidentally, as described above, the potentials of the dummy wires D1and D2 may be fixed.

Fifth Embodiment

The above description has used an example in which the dummy wires D1and D2 corresponding to the dummy wires 35 a and 36 a in the wiringlayers 35 and 36 are constituted by a sharing unit of two pixels×twopixels sharing the same FD contact or a sharing unit of two pixels×fourpixels sharing the FD at the same position. However, the dummy wires D1and D2 may have the same shape and position in a smaller unit within thesharing unit by the FD.

The solid-state image pickup element in FIG. 8 illustrates aconfiguration example of the solid-state image pickup element when thedummy wires D corresponding to the dummy wires 35 a and 36 a areprovided at the same position and in the same shape in pixel units.

In more detail, the solid-state image pickup element in FIG. 8illustrates a configuration example of the solid-state image pickupelement in which the dummy wire D which is the dummy wires 35 a and 36 ahaving a quadrangular shape is provided in the vicinity of the center ofeach pixel constituting the sharing unit.

Even with such a configuration, as a result, the dummy wires Dcorresponding to the dummy wires 35 a and 36 a are disposed in the sameshape and at the same position in units of two pixels×two pixels sharingthe same FD contact. This makes it possible to suppress characteristicfluctuations cause by capacitance fluctuations due to the dummy wire,while an affixing bonding strength of wafers is maintained, for a deviceconfigured by affixing a plurality of chips together to laminate.

Sixth Embodiment

The above description has used an example in which the dispositionpositions of the dummy wires 35 a and 36 a in the wiring layers 35 and36 are configured using the same shape and position at a pitch forsharing the same FD contact but additionally, the arrangement of thereal wire that actually transmits the pixel signal from the wiring layer35 to the wiring layer 36 may be also the same arrangement in units oftwo pixels×two pixels sharing the same FD contact.

FIG. 9 illustrates a configuration example of the solid-state imagepickup element in which the disposition position of the real wire isconfigured with the same position in units of two pixels×two pixelssharing the same FD contact in addition to the dummy wire Dcorresponding to the dummy wires 35 a and 36 a in the wiring layers 35and 36.

In more detail, in FIG. 9, a real wire L is disposed at the centerposition of two pixels×two pixels which is a unit for sharing the sameFD contact, while the dummy wire D constituted by the dummy wires 35 aand 36 a is arranged at each corner portion of two pixels×two pixelswhich is a unit for sharing the FD contact.

With such a configuration, the real wire L having a square shape isdisposed at the center position of two pixels×two pixels which is a unitfor sharing the same FD contact, while the dummy wire D constituted bythe dummy wires 35 a and 36 a having a square shape is arranged at eachcorner portion of two pixels×two pixels which is a unit for sharing theFD contact. This makes it possible to suppress characteristicfluctuations cause by capacitance fluctuations due to the dummy wire,while an affixing bonding strength of wafers is maintained, for a deviceconfigured by affixing a plurality of chips together to laminate.

Seventh Embodiment

The above description has used an example in which the real wire L isdisposed at the center position of two pixels×two pixels which is a unitfor sharing the FD contact, while the dummy wire D constituted by thedummy wires 35 a and 36 a is arranged at each corner portion of twopixels×two pixels which is a unit for sharing the FD contact. However,the dummy wire D and the real wire L are only required to be at the sameposition in units for sharing the FD contact.

FIG. 10 illustrates another configuration example when the dummy wire Dand the real wire L are at the same position in units of two pixels×twopixels which is a unit for sharing the FD contact.

That is, in FIG. 10, the dummy wires D are disposed substantially at thecenter positions of specific three pixels (R, Gr, and B pixels in FIG.10) of two pixels×two pixels which is a unit for sharing the same FDcontact, while the real wire L is disposed substantially at the centerposition of the other one pixel (Gb pixel in FIG. 10). That is, thedummy wire D and the real wire L that transmits the pixel signal fromthe wiring layer 35 to the wiring layer 36 are disposed in the sameshape and at the same position at the same specific position using twopixels×two pixels as a unit, which is a unit for sharing the same FDcontact. This makes it possible to suppress characteristic fluctuationscause by capacitance fluctuations due to the dummy wire, while anaffixing bonding strength of wafers is maintained, for a deviceconfigured by affixing a plurality of chips together to laminate.

Note that the shape, arrangement, size, whether to use the fixedpotential or floating in regard to the dummy wire D (the dummy wire 35 aon the upper chip side and the dummy wire 36 a on the lower chip side)and the real wire are not limited to the above-described embodiments butmay be combined in various variations. Therefore, when variations of thefirst to seventh embodiments are summarized from the points thereof, forexample, a combination of relationships as illustrated in FIG. 11 isobtained.

That is, the pitch of the dummy wire and the real wire may use any unitsuch as the FD contact, the sharing unit, or the pixel. In addition, theshape of the dummy wire and the real wire may be any shape includingsquare (left), rectangle (left), octagon, square (cut off), rectangle(cut off), and stripe (vertical or horizontal). Here, “left” meansforming the dummy wires and the real wires using a particular shape,whereas “cut off” means forming the dummy wires and the real wires usingthe shape of an outer circumferential portion obtained by cutting away aparticular shape. Furthermore, as for the combination of the upper andlower chips, all upper and lower chips may be the same or different inshape, size, and position. In addition, the potential of the dummy wiremay be floating or a fixed potential. Furthermore, regardless of an FDpixel pitch, a sharing unit pitch, or a pixel pitch, the presence orabsence of the real wire is irrelevant.

<Technique for Reducing Influence of Characteristic Fluctuations>

By making the dummy wire 35 a in the chip on the upper side larger thanthe dummy wire 36 a in the chip on the lower side, the influence due tocharacteristic fluctuations can be decreased even if a shift arises whenthe wiring layers 35 and 36 are affixed on the bonding surface F.

That is, by making the dummy wire 35 a larger than the dummy wire 36 ain the chip on the lower side, even in a case where the dummy wires 35 aand 36 a are affixed together at a proper position as illustrated in theupper part of FIG. 12 and a case where the wiring layer 36 is shifted tothe right with respect to the wiring layer 35 as illustrated in thelower part of FIG. 12, for example, the capacitance fluctuationsgenerated by the coupling of the dummy wire 35 a+the dummy wire 36 a issubstantially zero when seen from the dummy wire 35 b. Accordingly, theinfluence thereof on the characteristic fluctuations can be practicallyreduced even if a shift arises at the time of affixing the wiring layers35 and 36 together.

<Application to Device Other Than Solid-State Image Pickup Element>

The above description has used an example of the solid-state imagepickup element, but the present technology can be applied to anothersemiconductor device as long as the semiconductor device is configuredby affixing chips together to laminate.

For example, the present technology can be applied to a case where amemory is configured by laminating a plurality of chips.

That is, as illustrated in FIG. 13, in a case where a memory isconfigured by affixing a chip constituted by a substrate layer 51 and awiring layer 52 and a chip constituted by a wiring layer 53 and asubstrate layer 54 together at the bonding surface F, it is possible tosuppress characteristic fluctuations caused by capacitance fluctuationsdue to the dummy wire by arranging dummy wires 52 a and 53 a in linewith a pitch for repeating the unit cell MU.

In this case, application to a memory is possible as long as the memoryuses a unit cell and, specifically, the present technology can beapplied to, for example, a dynamic random access memory (DRAM) and aflash memory. In addition to the memory, the present technology can beadapted to, for example, any semiconductor device as long as thesemiconductor device is formed by repeatedly arranging unit cells.

<Example of Application to Electronic Apparatus>

The solid-state image pickup element described above can be applied tovarious electronic apparatuses, for example, an imaging device such as adigital still camera or a digital video camera, a mobile phone having animaging function, or another apparatus having an imaging function.

FIG. 14 is a block diagram illustrating a configuration example of animaging device serving as the electronic apparatus to which the presenttechnology is applied.

The imaging device 201 illustrated in FIG. 14 is configured by includingan optical system 202, a shutter device 203, a solid-state image pickupelement 204, a drive circuit 205, a signal processing circuit 206, amonitor 207, and a memory 208, and capable of capturing a still imageand a moving image.

The optical system 202 is configured by including one or a plurality oflenses and guides light (incident light) from a subject to thesolid-state image pickup element 204 to form an image on a lightreceiving surface of the solid-state image pickup element 204.

The shutter device 203 is arranged between the optical system 202 andthe solid-state image pickup element 204 and controls a lightirradiation period and a light shielding period to the solid-state imagepickup element 204 under the control of the drive circuit 1005.

The solid-state image pickup element 204 is constituted by a packageincluding the above-described solid-state image pickup element. Thesolid-state image pickup element 204 accumulates a signal charge for acertain period according to light formed on the light receiving surfacevia the optical system 202 and the shutter device 203. The signalcharges accumulated in the solid-state image pickup element 204 aretransferred in accordance with a drive signal (timing signal) suppliedfrom the drive circuit 205.

The drive circuit 205 outputs a drive signal for controlling a transferaction of the solid-state image pickup element 204 and a shutter actionof the shutter device 203 to drive the solid-state image pickup element204 and the shutter device 203.

The signal processing circuit 206 applies various types of signalprocessing to the signal charge output from the solid-state image pickupelement 204. An image (image data) obtained through the signalprocessing applied by signal processing circuit 206 is supplied to themonitor 207 to be displayed or supplied to the memory 208 to be stored(recorded).

Also in the imaging device 201 configured as described above, it ispossible to realize imaging with low noise at all pixels by applying thesolid-state image pickup element 1 instead of the above-describedsolid-state image pickup element 204.

<Example of Use of Solid-State Image Pickup Element>

FIG. 15 is a diagram illustrating an example of use in which theabove-described solid-state image pickup element is used.

For example, the above-described solid-state image pickup element can beused in various cases of sensing light such as visible light, infraredlight, ultraviolet light, and X-ray, as described below.

-   -   A device that captures an image to be used for viewing purposes,        such as digital cameras or portable apparatuses with a camera        function    -   A device used for traffic purposes, such as in-vehicle sensors        that capture images of the front, back, surroundings, inside,        and so on of an automobile for, for example, safe driving such        as automatic stop and recognition of the state by the driver, a        surveillance camera that monitors traveling vehicles and roads,        and a distance measuring sensor that measures a distance between        vehicles, and so on    -   A device used for home appliances such as TVs, refrigerators,        and air conditioners to capture an image of a gesture of a user        such that an apparatus is operated in accordance with the        gesture    -   A device used for medical and healthcare purposes, such as        endoscopes and devices that perform angiography by receiving        infrared light    -   A device used for security purposes, such as surveillance        cameras for crime prevention use and cameras for person        authentication use    -   A device used for cosmetic purposes, such as skin measuring        instruments that capture images of skin and microscopes that        capture images of the scalp    -   A device used for sports purposes, such as action cameras and        wearable cameras for sports use    -   A device used for agricultural purposes, such as cameras for        monitoring the condition of fields and crops

Note that the present technology can be also configured as describedbelow.

-   (1) A semiconductor device including two or more chips in which    wires that are electrically connected are formed on bonding surfaces    and the bonding surfaces opposing each other are bonded to be    laminated, in which

with respect to a region where the wires are periodically and repeatedlydisposed in predetermined units, a dummy wire is disposed on the bondingsurface at a pitch corresponding to the predetermined unit.

-   (2) The semiconductor device according to (1), in which

the semiconductor device is a solid-state image pickup element, and

with respect to a region where the wires are periodically and repeatedlydisposed in predetermined units for a pixel of the solid-state imagepickup element, the dummy wire is disposed on the bonding surface at apitch corresponding to the predetermined unit.

-   (3) The semiconductor device according to (2), in which

the dummy wire disposed on one of the bonding surfaces opposing eachother and the dummy wire disposed on another of the bonding surfacesopposing each other have substantially the same pattern.

-   (4) The semiconductor device according to (2), in which

the dummy wire disposed on one of the bonding surfaces opposing eachother and the dummy wire disposed on another of the bonding surfaceopposing each other have different patterns.

-   (5) The semiconductor device according to any one of (2) to (4), in    which

the predetermined unit for the pixel of the solid-state image pickupelement is a plurality of the pixels sharing a contact of the samefloating diffusion.

-   (6) The semiconductor device according to any one of (2) to (4), in    which

the predetermined unit for the pixel of the solid-state image pickupelement is a plurality of the pixels sharing the same floatingdiffusion.

-   (7) The semiconductor device according to (2) to (4), in which

the predetermined unit for the pixel of the solid-state image pickupelement is a single one of the pixels.

-   (8) The semiconductor device according to any one of (2) to (7), in    which

with respect to a region where the wires are periodically and repeatedlydisposed in the predetermined units for the pixel of the solid-stateimage pickup element, a real wire is disposed along with the dummy wireon the bonding surface at a pitch corresponding to the predeterminedunit.

-   (9) The semiconductor device according to any one of (1) to (7),    further including an electrode to which a predetermined voltage is    applied, in which

the dummy wire is fixed to the predetermined voltage applied from theelectrode.

-   (10) A solid-state image pickup element including two or more chips    in which wires that are electrically connected are formed on bonding    surfaces and the bonding surfaces opposing each other are bonded to    be laminated, in which

with respect to a region where the wires are periodically and repeatedlydisposed in predetermined units for a pixel, the dummy wire is disposedon the bonding surface at a pitch corresponding to the predeterminedunit.

-   (11) An imaging device including two or more chips in which wires    that are electrically connected are formed on bonding surfaces and    the bonding surfaces opposing each other are bonded to be laminated,    in which

with respect to a region where the wires are periodically and repeatedlydisposed in predetermined units for a pixel, the dummy wire is disposedon the bonding surface at a pitch corresponding to the predeterminedunit.

-   (12) An electronic apparatus including two or more chips in which    wires that are electrically connected are formed on bonding surfaces    and the bonding surfaces opposing each other are bonded to be    laminated, in which

with respect to a region where the wires are periodically and repeatedlydisposed in predetermined units for a pixel, the dummy wire is disposedon the bonding surface at a pitch corresponding to the predeterminedunit.

REFERENCE SIGNS LIST

-   11 Solid-state image pickup element-   31 Lens layer-   32 Color filter layer-   33 Light shielding wall layer-   33 a Light shielding wall-   34 Photoelectric change layer-   35 Wiring layer-   35 a, 35 b Dummy wire-   36 Wiring layer-   36 a, 36 b Dummy wire-   51 Substrate layer-   52 Wiring layer-   52 a, 52 b Dummy wiring layer-   53 Wiring layer-   53 a, 53 b Dummy wiring layer-   54 Substrate layer

1-12. (canceled)
 13. A semiconductor device comprising a first chip anda second chip, wherein the first chip comprises: a pixel regionincluding a plurality of electrically-connected wires periodically andrepeatedly disposed on a bonding surface in a predetermined unit in thepixel region, and a first dummy wire disposed on the bonding surface,wherein the first dummy wire is coupled to a second dummy wire of thesecond chip.
 14. The semiconductor device according to claim 13, whereinthe first dummy wire and the second dummy wire are disposed tocorrespond to at least a center part of the predetermined unit.
 15. Thesemiconductor device according to claim 13, wherein the bonding surfaceopposes a second bonding surface, and the second dummy wire is disposedon the second bonding surface.
 16. The semiconductor device according toclaim15, wherein a pattern of the first dummy wire is substantiallyidentical to a pattern of the second dummy wire.
 17. The semiconductordevice according to claim 15, wherein a pattern of the first dummy wireis different from a pattern of the second dummy wire.
 18. Thesemiconductor device according to claim 13, wherein the first dummy wireis disposed corresponding to a floating diffusion.
 19. The semiconductordevice according to claim 13, wherein a real wire of the plurality ofelectrically-connected wires is disposed on the bonding surface of thepixel region with the first dummy wire at a pitch corresponding to thepredetermined unit, wherein the real wire transmits a pixel signal. 20.An electronic apparatus comprising a semiconductor device, thesemiconductor device comprising a first chip and a second chip, thefirst chip comprising: a pixel region including a plurality ofelectrically-connected wires periodically and repeatedly disposed on abonding surface in a predetermined unit in the pixel region, and a firstdummy wire disposed on the bonding surface, wherein the first dummy wireis coupled to a second dummy wire of the second chip.
 21. The electronicapparatus according to claim 20, wherein the first dummy wire and thesecond dummy wire are disposed to correspond to at least a center partof the predetermined unit.
 22. The electronic apparatus according toclaim 20, wherein the bonding surface opposes a second bonding surface,and the second dummy wire is disposed on the second bonding surface. 23.The electronic apparatus according to claim 22, wherein a pattern of thefirst dummy wire is substantially identical to a pattern of the seconddummy wire.
 24. The electronic apparatus according to claim 22, whereina pattern of the first dummy wire is different from a pattern of thesecond dummy wire.
 25. The electronic apparatus according to claim 20,wherein the first dummy wire is disposed corresponding to a floatingdiffusion.
 26. The electronic apparatus according to claim 20, wherein areal wire of the plurality of electrically-connected wires is disposedon the bonding surface of the pixel region with the first dummy wire ata pitch corresponding to the predetermined unit, wherein the real wiretransmits a pixel signal.
 27. A solid-state image pickup elementcomprising a first chip and a second chip, wherein the first chipcomprises: a pixel region including a plurality ofelectrically-connected wires periodically and repeatedly disposed on abonding surface in a predetermined unit in the pixel region, and a firstdummy wire disposed on the bonding surface, wherein the first dummy wireis coupled to a second dummy wire of the second chip.
 28. The electronicapparatus according to claim 27, wherein the first dummy wire and thesecond dummy wire are disposed to correspond to at least a center partof the predetermined unit.
 29. The electronic apparatus according toclaim 27, wherein the bonding surface opposes a second bonding surface,and the second dummy wire is disposed on the second bonding surface. 30.The electronic apparatus according to claim 29, wherein a pattern of thefirst dummy wire is substantially identical to a pattern of the seconddummy wire.
 31. The electronic apparatus according to claim 29, whereina pattern of the first dummy wire is different from a pattern of thesecond dummy wire.
 32. The electronic apparatus according to claim 27,wherein the first dummy wire is disposed corresponding to a floatingdiffusion.